The present invention generally relates to a semiconductor memory device, and in particular to a semiconductor memory device such as a dynamic random access memory (DRAM) comprising one-transistor cell type memory cells. The present invention more particularly relates to a divided bit line type semiconductor memory device.
A semiconductor memory device such as a dynamic random access memory (hereafter abbreviated as DRAM) generally includes a memory cell array, a row decoder, a column decoder, an input/output (hereafter referred to as I/O) gate, a data bus and a sense amplifier. The cell array is configured by arranging memory cells each consisting of a transistor Q and a capacitor C at cross-points of word lines and bit lines. The row decoder selects one of the word lines corresponding to a row address supplied by an external circuit. The column decoder outputs a signal for selecting a pair of bit lines corresponding to a column address supplied by an external circuit. The I/O gate connects the gate corresponding to the pair of bit lines designated by the column decoder to the data bus. The sense amplifier senses and amplifies a difference in potential between the pair of bit lines.
The bit lines in the DRAM are generally formed with a plurality of pairs of bit lines. As well known, there are two types of pairs of bit lines, one of which is an open bit line type and the other is a folded bit line type. In the open bit line configuration, two bit lines forming one pair each extend from opposing sides of the sense amplifier, whereas in the folded bit line configuration, both the bit lines forming the pair extend from the same side of the sense amplifier.
Although the DRAM thus configured has advantages of a simple structure and a high integration density, it has the following disadvantages. That is, as the storage capacity increases, memory cells are minimized and correspondingly the capacity of the cell capacitor decreases. In this case, a C-ratio, which is defined as a ratio of the capacitance C.sub.BL of the bit line to the capacitance C.sub.CELL of the cell capacitance, is increased (degraded) as the memory cells are minimized, because the read-out operation of the DRAM depends on a distribution of the capacitance between the bit line and the memory cell. Therefore, it becomes difficult to generate the difference in potential between the pair of the bit lines. In addition, it becomes difficult to obtain a desired amplifying operation of the sense amplifier.
Hence, there has been proposed a solution that the bit lines are divided into two or more parts to thereby improve the C-ratio. The capacitance of each of the divided bit lines becomes 1/2, 1/4, . . . , as the bit lines are divided into two, four, . . . , so that the C-ratio can be decreased (improved). In addition, the division of the bit lines enables the sense amplifier to rapidly amplify the difference in potential between the pair of the bit lines, which makes possible a high-speed reading-out operation of the DRAM.
In the divided bit line type DRAM aforementioned, the sense amplifier positioned between adjacent pairs of divided bit lines is generally a flip-flop which is formed with n- or p-channel metal oxide semiconductor (hereafter referred to MOS) transistors. This means that the use of complementary MOS (hereafter referred to as CMOS) transistors has not yet been proposed in the divided bit line type DRAM. It should be noted that as will be shown later, a CMOS sense amplifier itself has been proposed in configurations other than the divided bit line type. However, as will be described later, a mere replacement of the sense amplifier formed with n- or p-channel transistors with the proposed one formed with CMOS transistors leads to problems of large power consumption.